Microcontroller PIC und Atmel AVR
Hast du die 10k in der Schaltung mal nachgemessen und die Verbindung Anfang-Ende?habe an den Pullup von 10kohm gedacht für die data Leitung (im Scope pink) da der controller diese per open collector nur auf low ziehen kann.
Hast du die 10k in der Schaltung mal nachgemessen und die Verbindung Anfang-Ende?
• MISO/PDO/PCINT3 – Port B, Bit 3
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is
enabled as a master, this pin is configured as an input regardless of the setting of
DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by
DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated
as long as the SS
pin is driven high. In this state, software may update the contents of
the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock
pulses on the SCK pin until the SS pin is driven low. As one byte has been completely
shifted, the end of Transmission Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE,
in the SPCR Register is set, an interrupt is requested. The Slave may continue to place
new data to be sent into SPDR before reading the incoming data. The last incoming
byte will be kept in the Buffer Register for later use.
22.3.1 Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS
) pin is always input. When
is held low, the SPI is activated, and MISO becomes an output if configured so by
the user. All other pins are inputs. When SS
is driven high, all pins are inputs, and the
SPI is passive, which means that it will not receive incoming data. Note that the SPI
logic will be reset once the SS
pin is driven high. The SS
pin is useful for packet/byte
synchronization to keep the slave bit counter synchronous with the master clock
generator. When the SS
pin is driven high, the SPI slave will immediately reset the send
and receive logic, and drop any partially received data in the Shift Register.
22.3.2 Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can
determine the direction of the SS
pin. If SS
is configured as an output, the pin is a
general output pin which does not affect the SPI system. Typically, the pin will be
driving the SS
pin of the SPI Slave. If SS
is configured as an input, it must be held high
to ensure Master SPI operation. If the SS
pin is driven low by peripheral circuitry when
the SPI is configured as a Master with the SS
pin defined as an input, the SPI system
interprets this as another master selecting the SPI as a slave and starting to send data
to it. To avoid bus contention, the SPI system takes the following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result
of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists
a possibility that SS
is driven low, the interrupt should always check that the MSTR bit
is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user
to re-enable SPI Master Mode
snipp hat geschrieben:Der MCU zieht die Leitung übrigens nicht hoch, aber wäre ja ne Idee gewesen.
snipp hat geschrieben:Ich habe keine Idee mehr, warum die Spannung einbricht bzw. der Ps2 Controller nicht antwortet. :/
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